The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a double patterning method.
Semiconductor technologies are continually progressing to smaller feature sizes, down to 65 nanometers, 45 nanometers, and beyond. A patterned photoresist layer used to produce such small feature sizes typically has a high aspect ratio. Maintaining a desired critical dimension (CD) can be very difficult for various reasons. For example, because resist materials are susceptible to the etching process, they may suffer from pattern collapse and CD degradation during a photolithography patterning process. When double patterning techniques are utilized, additional issues may be brought out, such as round corners, resist pattern collapse, etching resistance, poor topography, exposure focusing errors, high manufacturing costs, and low throughput.